Ignore cast expressions when generating VHDL.

[matthijs/master-project/cλash.git] / NormalizeTools.hs

diff --git a/NormalizeTools.hs b/NormalizeTools.hs
index c20c58349491ee5aa75a5fe8348fe1fa4623ca13..8e57ba8f2ec2446301ebcf22ec83e03f577470b7 100644 (file)
--- a/NormalizeTools.hs
+++ b/NormalizeTools.hs
@@ -147,6 +147,10 @@ subeverywhere trans (Var x) = return $ Var x
 subeverywhere trans (Lit x) = return $ Lit x
 subeverywhere trans (Type x) = return $ Type x
 
+subeverywhere trans (Cast expr ty) = do
+  expr' <- trans expr
+  return $ Cast expr' ty
+
 subeverywhere trans expr = error $ "NormalizeTools.subeverywhere Unsupported expression: " ++ show expr
 
 -- Apply the given transformation to all expressions, except for direct