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Don't propagate types with free tyvars.
[matthijs/master-project/cλash.git]
/
Main.hs
diff --git
a/Main.hs
b/Main.hs
index be0a0a077f5496d7c9f3c06daa4fd58ae12779b7..42818c0c26b986a514f4246d208337b6e8aa9d92 100644
(file)
--- a/
Main.hs
+++ b/
Main.hs
@@
-3,4
+3,4
@@
module Main where
import Translator
main = do
- makeVHDL "A
lu.hs" "exec
" True
\ No newline at end of file
+ makeVHDL "A
dders.hs" "highordtest2
" True
\ No newline at end of file