Make genMap support mapping applications.

[matthijs/master-project/cλash.git] / Main.hs

diff --git a/Main.hs b/Main.hs
index 078f46fe0807d2d902c332c3adb028ad3d47b579..42818c0c26b986a514f4246d208337b6e8aa9d92 100644 (file)
--- a/Main.hs
+++ b/Main.hs
@@ -3,4 +3,4 @@ module Main where
 import Translator
 
 main = do
-  makeVHDL "Adders.hs" "functiontest" True
\ No newline at end of file
+  makeVHDL "Adders.hs" "highordtest2" True
\ No newline at end of file