Add automated testbench generation according to supplied test input

[matthijs/master-project/cλash.git] / HighOrdAlu.hs

diff --git a/HighOrdAlu.hs b/HighOrdAlu.hs
index def77421281ce0362125c266f3887c9d86c9943b..1ead210f0bb82dd85ceae098bdd3fb89380b5cf8 100644 (file)
--- a/HighOrdAlu.hs
+++ b/HighOrdAlu.hs
@@ -1,3 +1,5 @@
+{-# LANGUAGE TemplateHaskell #-}
+
 module HighOrdAlu where
 
 import Prelude hiding (
@@ -7,6 +9,7 @@ import Bits
 import Types
 import Data.Param.TFVec
 import Data.RangedWord
+import CLasH.Translator.Annotations
 
 constant :: e -> Op D4 e
 constant e a b =
@@ -32,12 +35,21 @@ xhwor = hwor
 type Op n e = (TFVec n e -> TFVec n e -> TFVec n e)
 type Opcode = Bit
 
+{-# ANN sim_input TestInput#-}
+sim_input = [ (High,$(vectorTH [High,Low,Low,Low]),$(vectorTH [High,Low,Low,Low]))
+            , (High,$(vectorTH [High,High,High,High]),$(vectorTH [High,High,High,High]))
+            , (Low,$(vectorTH [High,Low,Low,High]),$(vectorTH [High,Low,High,Low]))]
+
+{-# ANN actual_alu InitState #-}
+initstate = High
+
 alu :: Op n e -> Op n e -> Opcode -> TFVec n e -> TFVec n e -> TFVec n e
 alu op1 op2 opc a b =
   case opc of
     Low -> op1 a b
     High -> op2 a b
 
-actual_alu :: Opcode -> TFVec D4 Bit -> TFVec D4 Bit -> TFVec D4 Bit
+{-# ANN actual_alu TopEntity #-}
+actual_alu :: (Opcode, TFVec D4 Bit, TFVec D4 Bit) -> TFVec D4 Bit
 --actual_alu = alu (constant Low) andop
-actual_alu = alu (anyset xhwor)  andop
+actual_alu (opc, a, b) = alu (anyset xhwor) (andop) opc a b