Ignore cast expressions when generating VHDL.

[matthijs/master-project/cλash.git] / GlobalNameTable.hs

diff --git a/GlobalNameTable.hs b/GlobalNameTable.hs
index 8c3faab22c66467362bacb2d64c2fdd165f5de00..cf585ea50a88607ef146f7654f2510a7ace02765 100644 (file)
--- a/GlobalNameTable.hs
+++ b/GlobalNameTable.hs
@@ -17,10 +17,17 @@ mkGlobalNameTable = Map.fromList
 
 globalNameTable :: NameTable
 globalNameTable = mkGlobalNameTable
-  [ ("!"              , (2, genExprFCall2L exId                           ) )
-  , ("head"           , (1, genExprFCall1L headId                         ) )
+  [ ("!"              , (2, genExprFCall exId                             ) )
+  , ("replace"        , (3, genExprFCall replaceId                        ) )
+  , ("head"           , (1, genExprFCall headId                           ) )
+  , ("last"           , (1, genExprFCall lastId                           ) )
+  , ("tail"           , (1, genExprFCall tailId                           ) )
+  , ("init"           , (1, genExprFCall initId                           ) )
+  , ("take"           , (2, genExprFCall takeId                           ) )
+  , ("drop"           , (2, genExprFCall dropId                           ) )
+  , ("+>"             , (2, genExprFCall plusgtId                         ) )
   , ("hwxor"          , (2, genExprOp2 AST.Xor                            ) )
   , ("hwand"          , (2, genExprOp2 AST.And                            ) )
-  , ("hwor"           , (2, genExprOp2 AST.And                            ) )
+  , ("hwor"           , (2, genExprOp2 AST.Or                             ) )
   , ("hwnot"          , (1, genExprOp1 AST.Not                            ) )
   ]