Add a is_FApp predicate.

[matthijs/master-project/cλash.git] / FlattenTypes.hs

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index d0076636bdcd07e266215b74e92e875e4f547e17..b7be4645d89e1df519487192268d48d4ab6e978c 100644 (file)
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -96,6 +96,12 @@ data SigDef =
     defDst :: SignalId
   } deriving (Show, Eq)
 
+-- | Is the given SigDef a FApp?
+is_FApp :: SigDef -> Bool
+is_FApp d = case d of  
+  (FApp _ _ _) -> True
+  _ -> False
+
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal
@@ -189,12 +195,16 @@ genSignalId use ty = do
   return n
 
 -- | Add a name hint to the given signal
-addNameHint :: SignalId -> String -> FlattenState ()
-addNameHint id hint = do
+addNameHint :: String -> SignalId -> FlattenState ()
+addNameHint hint id = do
   info <- getSignalInfo id
   let hints = nameHints info
-  let hints' = (hint:hints)
-  setSignalInfo id (info {nameHints = hints'})
+  if hint `elem` hints
+    then do
+      return ()
+    else do
+      let hints' = (hint:hints)
+      setSignalInfo id (info {nameHints = hints'})
 
 -- | Returns the SignalInfo for the given signal. Errors if the signal is not
 --   known in the session.