Let VHDL generate a typecast for SizedWord literals.

[matthijs/master-project/cλash.git] / Flatten.hs

diff --git a/Flatten.hs b/Flatten.hs
index e434f2e0862f1d5adffa272298f267d22cb46b5a..74b3232a338640a1372d120ce164b6b388be6b12 100644 (file)
--- a/Flatten.hs
+++ b/Flatten.hs
@@ -169,7 +169,7 @@ flattenExpr binds var@(Var id) =
           sig_id <- genSignalId SigInternal ty
           -- Add a name hint to the signal
           addNameHint (Name.getOccString id) sig_id
-          addDef (UncondDef (Right $ Literal lit) sig_id)
+          addDef (UncondDef (Right $ Literal lit Nothing) sig_id)
           return ([], Single sig_id)
     IdInfo.VanillaGlobal ->
       -- Treat references to globals as an application with zero elements
@@ -218,9 +218,12 @@ flattenExpr binds app@(App _ _) = do
         sig_id <- genSignalId SigInternal ty
         -- TODO: fromInteger is defined for more types than just SizedWord
         let len = sized_word_len ty
-        -- TODO: to_stdlogicvector doesn't work here, since SizedWord
-        -- translates to a different type...
-        addDef (UncondDef (Right $ Literal $ "to_stdlogicvector(to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ "))") sig_id)
+        -- Use a to_unsigned to translate the number (a natural) to an unsiged
+        -- (array of bits)
+        let lit_str = "to_unsigned(" ++ (show int) ++ ", " ++ (show len) ++ ")"
+        -- Set the signal to our literal unconditionally, but add the type so
+        -- the literal will be typecast to the proper type.
+        addDef $ UncondDef (Right $ Literal lit_str (Just ty)) sig_id
         return ([], Single sig_id)
       else
         flattenApplicationExpr binds (CoreUtils.exprType app) f args