Restructure a lot of VHDL generating code.

[matthijs/master-project/cλash.git] / CoreTools.hs

diff --git a/CoreTools.hs b/CoreTools.hs
index 3c26793c8c804ce7f9dd7262851565398638195d..c797bb7581fa3b615af426e1693f4ff6303235ae 100644 (file)
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@ -27,8 +27,10 @@ import qualified Unique
 import qualified CoreUtils
 import qualified CoreFVs
 
+-- Local imports
 import GhcTools
 import HsTools
+import Pretty
 
 -- | Evaluate a core Type representing type level int from the tfp
 -- library to a real int.
@@ -92,15 +94,19 @@ ranged_word_bound ty =
 tfvec_len :: Type.Type -> Int
 tfvec_len ty =
   eval_tfp_int len
-  where 
-    (tycon, args) = Type.splitTyConApp ty
+  where  
+    args = case Type.splitTyConApp_maybe ty of
+      Just (tycon, args) -> args
+      Nothing -> error $ "CoreTools.tfvec_len Not a vector type: " ++ (pprString ty)
     [len, el_ty] = args
     
 -- | Get the element type of a TFVec type
 tfvec_elem :: Type.Type -> Type.Type
 tfvec_elem ty = el_ty
   where
-    (tycon, args) = Type.splitTyConApp ty
+    args = case Type.splitTyConApp_maybe ty of
+      Just (tycon, args) -> args
+      Nothing -> error $ "CoreTools.tfvec_len Not a vector type: " ++ (pprString ty)
     [len, el_ty] = args
 
 -- Is this a wild binder?
@@ -142,3 +148,8 @@ is_applicable expr = is_fun expr || is_poly expr
 -- Does the given CoreExpr have any free type vars?
 has_free_tyvars :: CoreSyn.CoreExpr -> Bool
 has_free_tyvars = not . VarSet.isEmptyVarSet . (CoreFVs.exprSomeFreeVars Var.isTyVar)
+
+-- Turns a Var CoreExpr into the Id inside it. Will of course only work for
+-- simple Var CoreExprs, not complexer ones.
+exprToVar :: CoreSyn.CoreExpr -> Var.Id
+exprToVar (CoreSyn.Var id) = id