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Generate proper VHDL for top level bindings with no arguments.
[matthijs/master-project/cλash.git]
/
CoreTools.hs
diff --git
a/CoreTools.hs
b/CoreTools.hs
index eae4122deff7425570ea5b232d4545ede76d46ac..bd6f329c537ea93842bf5b221998cf47fb69085c 100644
(file)
--- a/
CoreTools.hs
+++ b/
CoreTools.hs
@@
-222,4
+222,4
@@
getLiterals :: CoreSyn.CoreExpr -> [CoreSyn.CoreExpr]
getLiterals app@(CoreSyn.App _ _) = literals
where
(CoreSyn.Var f, args) = CoreSyn.collectArgs app
- literals = filter (is_lit) args
\ No newline at end of file
+ literals = filter (is_lit) args