Put the Builders in the VHDLSession.

[matthijs/master-project/cλash.git] / CoreTools.hs

diff --git a/CoreTools.hs b/CoreTools.hs
index 85c398ab7c2777bb920c749033f28caa2594d6c4..b08f3ce9897d65b607c14a7ed3db2ed8eca195ad 100644 (file)
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@ -95,6 +95,13 @@ tfvec_len ty =
   where 
     (tycon, args) = Type.splitTyConApp ty
     [len, el_ty] = args
+    
+-- | Get the element type of a TFVec type
+tfvec_elem :: Type.Type -> Type.Type
+tfvec_elem ty = el_ty
+  where
+    (tycon, args) = Type.splitTyConApp ty
+    [len, el_ty] = args
 
 -- Is this a wild binder?
 is_wild :: CoreSyn.CoreBndr -> Bool
@@ -135,3 +142,8 @@ is_applicable expr = is_fun expr || is_poly expr
 -- Does the given CoreExpr have any free type vars?
 has_free_tyvars :: CoreSyn.CoreExpr -> Bool
 has_free_tyvars = not . VarSet.isEmptyVarSet . (CoreFVs.exprSomeFreeVars Var.isTyVar)
+
+-- Turns a Var CoreExpr into the Id inside it. Will of course only work for
+-- simple Var CoreExprs, not complexer ones.
+exprToVar :: CoreSyn.CoreExpr -> Var.Id
+exprToVar (CoreSyn.Var id) = id