Generalize VHDL type creation for SizedWord and FSVec.

[matthijs/master-project/cλash.git] / CoreTools.hs

diff --git a/CoreTools.hs b/CoreTools.hs
index 06b7a62388a4c00446737e026bed7e03bf974d4b..3d3828b45b8c150d4c552759e6202a590a21c7fa 100644 (file)
--- a/CoreTools.hs
+++ b/CoreTools.hs
@@ -69,3 +69,11 @@ eval_type_level_int ty =
 
     core <- toCore [] app
     execCore core 
+
+-- | Get the length of a FSVec type
+fsvec_len :: Type.Type -> Int
+fsvec_len ty =
+  eval_type_level_int len
+  where 
+    (tycon, args) = Type.splitTyConApp ty
+    [len, el_ty] = args