module Alu where
import Bits
import qualified Sim
+import Data.SizedWord
+import Types
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
-dontcare = DontCare
+dontcare = Low
program = [
-- (addr, we, op)
]
--initial_state = (Regs Low High, Low, Low)
-initial_state = ((Low, High), Low, Low)
+initial_state = ((0, 1), 0, 0)
+type Word = SizedWord D4
-- Register bank
-
type RegAddr = Bit
-type RegisterBankState = (Bit, Bit)
+type RegisterBankState = (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
register_bank ::
- (RegAddr, Bit, Bit) -> -- (addr, we, d)
+ (RegAddr, Bit, Word) -> -- (addr, we, d)
RegisterBankState -> -- s
- (RegisterBankState, Bit) -- (s', o)
+ (RegisterBankState, Word) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
--(s, r0 s)
(s, snd s)
register_bank (addr, High, d) s = -- Write
- (s', dontcare)
+ (s', 0)
where
--Regs r0 r1 = s
(r0, r1) = s
- r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
- r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
--s' = Regs r0' r1'
s' = (r0', r1')
type AluOp = Bit
-alu :: AluOp -> Bit -> Bit -> Bit
-alu High a b = a `hwand` b
-alu Low a b = a `hwor` b
+alu :: AluOp -> Word -> Word -> Word
+{-# NOINLINE alu #-}
+--alu High a b = a `hwand` b
+--alu Low a b = a `hwor` b
+alu High a b = a + b
+alu Low a b = a - b
-type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (Bit))
+type ExecState = (RegisterBankState, Word, Word)
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
-- Read & Exec
exec (addr, we, op) s =