-module Alu (main) where
+module Alu where
import Bits
import qualified Sim
+import Data.SizedWord
+import Types
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
+dontcare = Low
+
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
(Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
- (Low, High, DontCare), -- r0 = z (1)
+ (Low, High, dontcare), -- r0 = z (1)
(High, Low, High), -- z = r1 and t (0); t = r1 (1)
- (High, High, DontCare) -- r1 = z (0)
+ (High, High, dontcare) -- r1 = z (0)
]
-initial_state = ((Low, High), (), Low, Low)
-
---
---
+--initial_state = (Regs Low High, Low, Low)
+initial_state = ((0, 1), 0, 0)
+type Word = SizedWord D4
+-- Register bank
type RegAddr = Bit
-type RegisterBankState = (Bit, Bit)
+type RegisterBankState = (Word, Word)
+--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+
register_bank ::
- (RegAddr, Bit, Bit) -> -- (addr, we, d)
+ (RegAddr, Bit, Word) -> -- (addr, we, d)
RegisterBankState -> -- s
- (RegisterBankState, Bit) -- (s', o)
+ (RegisterBankState, Word) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
+ --(s, r0 s)
(s, fst s)
register_bank (High, Low, _) s = -- Read r1
+ --(s, r1 s)
(s, snd s)
register_bank (addr, High, d) s = -- Write
- (s', DontCare)
+ (s', 0)
where
+ --Regs r0 r1 = s
(r0, r1) = s
- r0' = if addr == Low then d else r0
- r1' = if addr == High then d else r1
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
+ --s' = Regs r0' r1'
s' = (r0', r1')
-type AluState = ()
+-- ALU
+
type AluOp = Bit
-alu :: (AluOp, Bit, Bit) -> AluState -> (AluState, Bit)
-alu (High, a, b) s = ((), a `hwand` b)
-alu (Low, a, b) s = ((), a `hwor` b)
+alu :: AluOp -> Word -> Word -> Word
+{-# NOINLINE alu #-}
+--alu High a b = a `hwand` b
+--alu Low a b = a `hwor` b
+alu High a b = a + b
+alu Low a b = a - b
-type ExecState = (RegisterBankState, AluState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+type ExecState = (RegisterBankState, Word, Word)
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
-- Read & Exec
-exec (addr, Low, op) s =
- (s', ())
- where
- (reg_s, alu_s, t, z) = s
- (reg_s', t') = register_bank (addr, Low, DontCare) reg_s
- (alu_s', z') = alu (op, t', t) alu_s
- s' = (reg_s', alu_s', t', z')
-
--- Write
-exec (addr, High, op) s =
- (s', ())
+exec (addr, we, op) s =
+ (s', z')
where
- (reg_s, alu_s, t, z) = s
- (reg_s', _) = register_bank (addr, High, z) reg_s
- s' = (reg_s', alu_s, t, z)
+ (reg_s, t, z) = s
+ (reg_s', t') = register_bank (addr, we, z) reg_s
+ z' = alu op t' t
+ s' = (reg_s', t', z')
-- vim: set ts=8 sw=2 sts=2 expandtab: