main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
-dontcare = DontCare
+dontcare = Low
program = [
-- (addr, we, op)
where
--Regs r0 r1 = s
(r0, r1) = s
- r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
- r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
--s' = Regs r0' r1'
s' = (r0', r1')
type AluOp = Bit
alu :: AluOp -> Bit -> Bit -> Bit
+{-# NOINLINE alu #-}
alu High a b = a `hwand` b
alu Low a b = a `hwor` b