(High, High, dontcare) -- r1 = z (0)
]
-initial_state = (Regs Low High, Low, Low)
+--initial_state = (Regs Low High, Low, Low)
+initial_state = ((Low, High), Low, Low)
-- Register bank
type RegAddr = Bit
---type RegisterBankState = (Bit, Bit)
-data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+type RegisterBankState = (Bit, Bit)
+--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
register_bank ::
(RegAddr, Bit, Bit) -> -- (addr, we, d)
(RegisterBankState, Bit) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
- (s, r0 s)
+ --(s, r0 s)
+ (s, fst s)
register_bank (High, Low, _) s = -- Read r1
- (s, r1 s)
+ --(s, r1 s)
+ (s, snd s)
register_bank (addr, High, d) s = -- Write
(s', dontcare)
where
- Regs r0 r1 = s
- r0' = if addr == Low then d else r0
- r1' = if addr == High then d else r1
- s' = Regs r0' r1'
+ --Regs r0 r1 = s
+ (r0, r1) = s
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
+ --s' = Regs r0' r1'
+ s' = (r0', r1')
-- ALU
type AluOp = Bit
alu :: AluOp -> Bit -> Bit -> Bit
+{-# NOINLINE alu #-}
alu High a b = a `hwand` b
alu Low a b = a `hwor` b
type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (Bit))
-- Read & Exec
-exec (addr, Low, op) s =
- (s', ())
+exec (addr, we, op) s =
+ (s', z')
where
(reg_s, t, z) = s
- (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+ (reg_s', t') = register_bank (addr, we, z) reg_s
z' = alu op t' t
s' = (reg_s', t', z')
--- Write
-exec (addr, High, op) s =
- (s', ())
- where
- (reg_s, t, z) = s
- (reg_s', _) = register_bank (addr, High, z) reg_s
- s' = (reg_s', t, z)
-
-- vim: set ts=8 sw=2 sts=2 expandtab: