main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
-dontcare = DontCare
+dontcare = Low
program = [
-- (addr, we, op)
where
--Regs r0 r1 = s
(r0, r1) = s
- r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
- r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
--s' = Regs r0' r1'
s' = (r0', r1')
type AluOp = Bit
alu :: AluOp -> Bit -> Bit -> Bit
+{-# NOINLINE alu #-}
alu High a b = a `hwand` b
alu Low a b = a `hwor` b
-salu :: AluOp -> Bit -> Bit -> () -> ((), Bit)
-salu High a b s = (s, a `hwand` b)
-salu Low a b s = (s, a `hwor` b)
-
type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (Bit))
-- Read & Exec
-exec (addr, Low, op) s =
- (s', ())
+exec (addr, we, op) s =
+ (s', z')
where
(reg_s, t, z) = s
- (reg_s', t') = register_bank (addr, Low, dontcare) reg_s
+ (reg_s', t') = register_bank (addr, we, z) reg_s
z' = alu op t' t
s' = (reg_s', t', z')
--- Write
-exec (addr, High, op) s =
- (s', ())
- where
- (reg_s, t, z) = s
- (reg_s', _) = register_bank (addr, High, z) reg_s
- s' = (reg_s', t, z)
-
-- vim: set ts=8 sw=2 sts=2 expandtab: