Make SignalNameMap always map VHDLId's.

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index c2810d5b397af025816fa3e0ed5a87e95163ab0d..f32f5d4f9fd89acaa71d4535c072dafeb5f78361 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -1,8 +1,9 @@
 module Adders where
 import Bits
+import qualified Sim
 import Language.Haskell.Syntax
 
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
@@ -18,6 +19,14 @@ wire a = a
 inv :: Bit -> Bit
 inv a = hwnot a
 
+-- Not really an adder either, but a slightly more complex example
+invinv :: Bit -> Bit
+invinv a = hwnot (hwnot a)
+
+-- Not really an adder either, but a slightly more complex example
+dup :: Bit -> (Bit, Bit)
+dup a = (a, a)
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
@@ -34,8 +43,9 @@ half_adder (a, b) =
 full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
 full_adder (a, b, cin) = (s, c)
   where
-    s = a `hwxor` b `hwxor` cin
-    c = a `hwand` b `hwor` (cin `hwand` (a `hwxor` b))
+    (s1, c1) = half_adder(a, b)
+    (s, c2)  = half_adder(s1, cin)
+    c        = c1 `hwor` c2
 
 -- Four bit adder
 -- Explicit version