Make SignalNameMap always map VHDLId's.

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index 71d38dc4197293febaaca3917998fc8cf94841e2..f32f5d4f9fd89acaa71d4535c072dafeb5f78361 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -1,8 +1,9 @@
 module Adders where
 import Bits
+import qualified Sim
 import Language.Haskell.Syntax
 
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
@@ -42,9 +43,9 @@ half_adder (a, b) =
 full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
 full_adder (a, b, cin) = (s, c)
   where
-    x = a `hwxor` b
-    s = x `hwxor` cin
-    c = a `hwand` b `hwor` (cin `hwand` x)
+    (s1, c1) = half_adder(a, b)
+    (s, c2)  = half_adder(s1, cin)
+    c        = c1 `hwor` c2
 
 -- Four bit adder
 -- Explicit version