module Adders where
import Bits
+import qualified Sim
import Language.Haskell.Syntax
+import Data.TypeLevel
+import qualified Data.Param.FSVec as FSVec
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
+
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
+stateless f = \i s -> (s, f i)
show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
where
b = [Low, Low, Low, High]
(s, c) = f (a, b)
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
-- Not really an adder, but this is nice minimal hardware description
wire :: Bit -> Bit
wire a = a
+bus :: (Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec D4 -> BitVec D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+ --FSVec.map hwnot v
+ inv_n_rec v
+
+class Inv vec where
+ inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+ inv_n_rec v =
+ h FSVec.+> t
+ where
+ h = FSVec.head v
+ t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+ inv_n_rec v = v
+-}
-- Not really an adder either, but a slightly more complex example
inv :: Bit -> Bit
inv a = hwnot a
dup :: Bit -> (Bit, Bit)
dup a = (a, a)
+-- Not really an adder either, but a simple stateful example (D-flipflop)
+dff :: Bit -> Bit -> (Bit, Bit)
+dff d s = (s', q)
+ where
+ q = s
+ s' = d
+
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter a s =
+ (s', o)
+ where
+ s' = (a, b, c, d)
+ (b, c, d, o) = s
+
-- Combinatoric stateless no-carry adder
-- A -> B -> S
no_carry_adder :: (Bit, Bit) -> Bit
-- Combinatoric stateless half adder
-- A -> B -> (S, C)
half_adder :: (Bit, Bit) -> (Bit, Bit)
+{-# NOINLINE half_adder #-}
half_adder (a, b) =
( a `hwxor` b, a `hwand` b )
full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
full_adder (a, b, cin) = (s, c)
where
- x = a `hwxor` b
- s = x `hwxor` cin
- c = a `hwand` b `hwor` (cin `hwand` x)
+ (s1, c1) = half_adder(a, b)
+ (s, c2) = half_adder(s1, cin)
+ c = c1 `hwor` c2
+
+sfull_adder = stateless full_adder
-- Four bit adder
-- Explicit version