We now output VHDL types in the correct order

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index d4c43ca173450c14892dbfe92b57b478bcf8db63..6ada7df0f58d522c73522df6a3014c8944eb047c 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -10,6 +10,7 @@ import Prelude hiding (
 import Language.Haskell.Syntax
 import Types
 import Data.Param.TFVec
+import Data.RangedWord
 
 mainIO f = Sim.simulateIO (Sim.stateless f) ()
 
@@ -171,8 +172,15 @@ highordtest = \x ->
              in
                 \c d -> op' d c
 
-functiontest :: TFVec D4 Bit -> Bit
-functiontest = \v -> let r = head v in r
+xand a b = hwand a b
+
+functiontest :: TFVec D4 (TFVec D3 Bit) -> (TFVec D12 Bit, TFVec D3 Bit)
+functiontest = \v -> let r = (concat v, head v) in r
+
+xhwnot x = hwnot x
+
+maptest :: TFVec D4 Bit -> TFVec D4 Bit
+maptest = \v -> let r = map xhwnot v in r
 
 highordtest2 = \a b ->
          case a of