We now output VHDL types in the correct order

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index b17f744c0fbea1548e70cc341add975c9d99f089..6ada7df0f58d522c73522df6a3014c8944eb047c 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -174,8 +174,8 @@ highordtest = \x ->
 
 xand a b = hwand a b
 
-functiontest :: TFVec D4 Bit -> TFVec D4 Bit -> TFVec D4 (Bit, Bit)
-functiontest = \v1 v2 -> let r = zip v1 v2 in r
+functiontest :: TFVec D4 (TFVec D3 Bit) -> (TFVec D12 Bit, TFVec D3 Bit)
+functiontest = \v -> let r = (concat v, head v) in r
 
 xhwnot x = hwnot x