Add a two-port mux hardware model.

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index f35021c96fec00580168dc54c2ef4a2f7fe715a9..4745d8cd66b1984ae6e119f2e1e5399f38110ea2 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -1,8 +1,14 @@
 module Adders where
 import Bits
+import qualified Sim
 import Language.Haskell.Syntax
 
-main = do show_add exp_adder; show_add rec_adder;
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
+
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
+stateless f = \i s -> (s, f i)
 
 show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
   where
@@ -10,6 +16,10 @@ show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displ
     b = [Low, Low, Low, High]
     (s, c) = f (a, b)
 
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
 -- Not really an adder, but this is nice minimal hardware description
 wire :: Bit -> Bit
 wire a = a
@@ -26,6 +36,21 @@ invinv a = hwnot (hwnot a)
 dup :: Bit -> (Bit, Bit)
 dup a = (a, a)
 
+-- Not really an adder either, but a simple stateful example (D-flipflop)
+dff :: Bit -> Bit -> (Bit, Bit)
+dff d s = (s', q)
+  where
+    q = s
+    s' = d
+
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter a s =
+  (s', o)
+  where
+    s' = (a, b, c, d)
+    (b, c, d, o) = s
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
@@ -46,6 +71,8 @@ full_adder (a, b, cin) = (s, c)
     (s, c2)  = half_adder(s1, cin)
     c        = c1 `hwor` c2
 
+sfull_adder = stateless full_adder
+
 -- Four bit adder
 -- Explicit version
 -- [a] -> [b] -> ([s], cout)