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Fix vhdl type generation of index type, as upper bound is now exclusive
[matthijs/master-project/cλash.git]
/
clash
/
CLasH
/
VHDL
/
VHDLTools.hs
diff --git
a/clash/CLasH/VHDL/VHDLTools.hs
b/clash/CLasH/VHDL/VHDLTools.hs
index a70036ef33b56ff60816390b43505b7f7fcb6e77..8cb2f5e5881ebf022d91dd829de2707f2d0ebe7f 100644
(file)
--- a/
clash/CLasH/VHDL/VHDLTools.hs
+++ b/
clash/CLasH/VHDL/VHDLTools.hs
@@
-346,7
+346,8
@@
mkHTypeEither' ty | ty_has_free_tyvars ty = return $ Left $ "\nVHDLTools.mkHType
return $ Right $ SizedIType len
"Index" -> do
bound <- tfp_to_int (ranged_word_bound_ty ty)
return $ Right $ SizedIType len
"Index" -> do
bound <- tfp_to_int (ranged_word_bound_ty ty)
- return $ Right $ RangedWType bound
+ -- Upperbound is exclusive, hence the -1
+ return $ Right $ RangedWType (bound - 1)
otherwise ->
mkTyConHType tycon args
Nothing -> return $ Left $ "\nVHDLTools.mkHTypeEither': Do not know what to do with type: " ++ pprString ty
otherwise ->
mkTyConHType tycon args
Nothing -> return $ Left $ "\nVHDLTools.mkHTypeEither': Do not know what to do with type: " ++ pprString ty