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Add resetn ports
[matthijs/master-project/cλash.git]
/
cλash
/
CLasH
/
VHDL
/
VHDLTools.hs
diff --git
a/cλash/CLasH/VHDL/VHDLTools.hs
b/cλash/CLasH/VHDL/VHDLTools.hs
index 0d95f55425c90ec9198a93bd1dbc46ee2a108b2c..e5445a8eca7c21622d64d7b02ce5761204bae77f 100644
(file)
--- a/
cλash/CLasH/VHDL/VHDLTools.hs
+++ b/
cλash/CLasH/VHDL/VHDLTools.hs
@@
-119,7
+119,8
@@
mkComponentInst label entity_id portassigns = AST.CSISm compins
where
-- We always have a clock port, so no need to map it anywhere but here
clk_port = mkAssocElem clockId (idToVHDLExpr clockId)
where
-- We always have a clock port, so no need to map it anywhere but here
clk_port = mkAssocElem clockId (idToVHDLExpr clockId)
- compins = AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect (portassigns ++ [clk_port]))
+ resetn_port = mkAssocElem resetId (idToVHDLExpr resetId)
+ compins = AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect (portassigns ++ [clk_port,resetn_port]))
-----------------------------------------------------------------------------
-- Functions to generate VHDL Exprs
-----------------------------------------------------------------------------
-- Functions to generate VHDL Exprs