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Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
[matthijs/master-project/cλash.git]
/
cλash
/
CLasH
/
VHDL
/
VHDLTools.hs
diff --git
a/cλash/CLasH/VHDL/VHDLTools.hs
b/cλash/CLasH/VHDL/VHDLTools.hs
index e273da8bd3a9f26512389ea468cda228d2adcac8..cff65a68606a0a508ff05d8e882dab2ac49a981a 100644
(file)
--- a/
cλash/CLasH/VHDL/VHDLTools.hs
+++ b/
cλash/CLasH/VHDL/VHDLTools.hs
@@
-290,7
+290,8
@@
vhdl_ty_either tything =
Just ty -> vhdl_ty_either' ty
vhdl_ty_either' :: Type.Type -> TypeSession (Either String (Maybe AST.TypeMark))
Just ty -> vhdl_ty_either' ty
vhdl_ty_either' :: Type.Type -> TypeSession (Either String (Maybe AST.TypeMark))
-vhdl_ty_either' ty = do
+vhdl_ty_either' ty | ty_has_free_tyvars ty = return $ Left $ "VHDLTools.vhdl_ty_either': Cannot create type: type has free type variables: " ++ pprString ty
+ | otherwise = do
typemap <- getA tsTypes
htype_either <- mkHType ty
case htype_either of
typemap <- getA tsTypes
htype_either <- mkHType ty
case htype_either of