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TFVec builtin should now completely work
[matthijs/master-project/cλash.git]
/
cλash
/
CLasH
/
VHDL
/
VHDLTools.hs
diff --git
a/cλash/CLasH/VHDL/VHDLTools.hs
b/cλash/CLasH/VHDL/VHDLTools.hs
index 412e0c4a2dfa26193b33777f19282b169c3be8c0..9c10afd93349c805eb676bf36f4ec41f03b77db7 100644
(file)
--- a/
cλash/CLasH/VHDL/VHDLTools.hs
+++ b/
cλash/CLasH/VHDL/VHDLTools.hs
@@
-108,6
+108,10
@@
mkAssocElemIndexed :: AST.VHDLId -> AST.VHDLId -> AST.VHDLId -> AST.AssocElem
mkAssocElemIndexed port signal index = Just port AST.:=>: (AST.ADName (AST.NIndexed (AST.IndexedName
(AST.NSimple signal) [AST.PrimName $ AST.NSimple index])))
mkAssocElemIndexed port signal index = Just port AST.:=>: (AST.ADName (AST.NIndexed (AST.IndexedName
(AST.NSimple signal) [AST.PrimName $ AST.NSimple index])))
+-- | Create an aggregate signal
+mkAggregateSignal :: [AST.Expr] -> AST.Expr
+mkAggregateSignal x = AST.Aggregate (map (\z -> AST.ElemAssoc Nothing z) x)
+
mkComponentInst ::
String -- ^ The portmap label
-> AST.VHDLId -- ^ The entity name
mkComponentInst ::
String -- ^ The portmap label
-> AST.VHDLId -- ^ The entity name