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Add some gt,lt,gteq and lteq boolean operators
[matthijs/master-project/cλash.git]
/
cλash
/
CLasH
/
VHDL
/
Generate.hs
diff --git
a/cλash/CLasH/VHDL/Generate.hs
b/cλash/CLasH/VHDL/Generate.hs
index d1bf3751e3209dc0d1b8b8f8453bdb225ba12b57..1e6f28ffca0e33b7fb4f562889483aef0d4847a6 100644
(file)
--- a/
cλash/CLasH/VHDL/Generate.hs
+++ b/
cλash/CLasH/VHDL/Generate.hs
@@
-167,16
+167,18
@@
mkStateProcSm ::
mkStateProcSm (old, new) = do
nonempty <- hasNonEmptyType old
if nonempty
mkStateProcSm (old, new) = do
nonempty <- hasNonEmptyType old
if nonempty
- then return [AST.CSPSm $ AST.ProcSm label [cl
k
] [statement]]
+ then return [AST.CSPSm $ AST.ProcSm label [cl
ockId,resetId
] [statement]]
else return []
where
label = mkVHDLBasicId $ "state"
else return []
where
label = mkVHDLBasicId $ "state"
- clk = mkVHDLBasicId "clock"
rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
- assign = AST.SigAssign (varToVHDLName old) wform
- rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
- statement = AST.IfSm rising_edge_clk [assign] [] Nothing
+ clk_assign = AST.SigAssign (varToVHDLName old) wform
+ rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
+ resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
+ reset_statement = []
+ clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
+ statement = AST.IfSm resetn_is_low reset_statement clk_statement Nothing
-- | Transforms a core binding into a VHDL concurrent statement
-- | Transforms a core binding into a VHDL concurrent statement
@@
-879,7
+881,7
@@
genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
wform = AST.Wform [AST.WformElem data_in Nothing]
ramassign = AST.SigAssign ramloc wform
rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
wform = AST.Wform [AST.WformElem data_in Nothing]
ramassign = AST.SigAssign ramloc wform
rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
- statement = AST.IfSm (AST.And rising_edge_clk
(wrenable AST.:=: AST.PrimLit "'1'")
) [ramassign] [] Nothing
+ statement = AST.IfSm (AST.And rising_edge_clk
wrenable
) [ramassign] [] Nothing
-----------------------------------------------------------------------------
-- Function to generate VHDL for applications
-----------------------------------------------------------------------------
-- Function to generate VHDL for applications
@@
-1444,6
+1446,10
@@
globalNameTable = Map.fromList
, (hwnotId , (1, genOperator1 AST.Not ) )
, (equalityId , (2, genOperator2 (AST.:=:) ) )
, (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
, (hwnotId , (1, genOperator1 AST.Not ) )
, (equalityId , (2, genOperator2 (AST.:=:) ) )
, (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
+ , (ltId , (2, genOperator2 (AST.:<:) ) )
+ , (lteqId , (2, genOperator2 (AST.:<=:) ) )
+ , (gtId , (2, genOperator2 (AST.:>:) ) )
+ , (gteqId , (2, genOperator2 (AST.:>=:) ) )
, (boolOrId , (2, genOperator2 AST.Or ) )
, (boolAndId , (2, genOperator2 AST.And ) )
, (plusId , (2, genOperator2 (AST.:+:) ) )
, (boolOrId , (2, genOperator2 AST.Or ) )
, (boolAndId , (2, genOperator2 AST.And ) )
, (plusId , (2, genOperator2 (AST.:+:) ) )