- ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMap -- A mapping of the function result to port names
+ ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
+ ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-- A map of a builtin function to VHDL function builder
type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
-- A map of a builtin function to VHDL function builder
type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
- vsSignatures_ :: SignatureMap
+ vsSignatures_ :: SignatureMap,
+ -- | A map of Vector HsFunctions -> VHDL function call
+ vsNameTable_ :: NameTable