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Add getGlobalBinders accessor.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index 33010822b9ace9ec74e0002e0ba015fd2643254b..e517a8ba08166d6c5800bdb5d4f41b3e4ab74876 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-12,6
+12,7
@@
import qualified Data.Accessor.Template
-- GHC API imports
import qualified Type
-- GHC API imports
import qualified Type
+import qualified CoreSyn
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
@@
-30,8
+31,8
@@
type VHDLSignalMap = HsValueMap VHDLSignalMapElement
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
- ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMap -- A mapping of the function result to port names
+ ent_args :: [VHDLSignalMap
Element
], -- A mapping of each function argument to port names
+ ent_res :: VHDLSignalMap
Element
-- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
@@
-44,15
+45,25
@@
instance Ord OrdType where
-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
-- A map of a Core type to the corresponding type name
type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+
-- A map of a Haskell function to a hardware signature
-- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+type SignatureMap = Map.Map String Entity
+
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
- vsTypes_ :: TypeMap,
+ vsTypes_ :: TypeMap,
+ -- | A map of vector Core type -> VHDL type function
+ vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
- vsSignatures_ :: SignatureMap
+ vsSignatures_ :: SignatureMap,
+ -- | A map of Vector HsFunctions -> VHDL function call
+ vsNameTable_ :: NameTable
}
-- Derive accessors
}
-- Derive accessors