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Generate vector functions on demand.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index b3eaa9201f9c7bfc1b2147caba773395ee31cbc7..d23daea033d77b38710b5fe6c09fcbfaae2be62f 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-48,18
+48,14
@@
type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
-- A map of Elem types to the corresponding VHDL Id for the Vector
type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
-- A map of Elem types to the corresponding VHDL Id for the Vector
type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
--- A map of a vector Core type to the coressponding VHDL functions
-type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+-- A map of a vector Core element type and function name to the coressponding
+-- VHDLId of the function and the function body.
+type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
-
--- A map of a builtin function to VHDL function builder
-type NameTable = Map.Map String (Int, Builder )
-
-data VHDLSession = VHDLSession {
+data VHDLState = VHDLState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A map of Elem types -> VHDL Vector Id
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A map of Elem types -> VHDL Vector Id
@@
-68,18
+64,21
@@
data VHDLSession = VHDLSession {
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
- vsSignatures_ :: SignatureMap,
- -- | A map of Vector HsFunctions -> VHDL function call
- vsNameTable_ :: NameTable
+ vsSignatures_ :: SignatureMap
}
-- Derive accessors
}
-- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLS
ession
)
+$( Data.Accessor.Template.deriveAccessors ''VHDLS
tate
)
-- | The state containing a VHDL Session
-- | The state containing a VHDL Session
-type VHDLS
tate = State.State VHDLSession
+type VHDLS
ession = State.State VHDLState
-- | A substate containing just the types
type TypeState = State.State TypeMap
-- | A substate containing just the types
type TypeState = State.State TypeMap
+type Builder = Either (CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, Builder )
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: