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Added subtype declarations to TypeMap, removed SubtypeMap.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index 784b09706e6a6742a4fb504640983e8973349225..cc842897a873f28416974c98fc212be9609eca85 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-43,17
+43,27
@@
instance Ord OrdType where
compare (OrdType a) (OrdType b) = Type.tcCmpType a b
-- A map of a Core type to the corresponding type name
compare (OrdType a) (OrdType b) = Type.tcCmpType a b
-- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map String Entity
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map String Entity
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
+
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
data VHDLSession = VHDLSession {
-- | A map of Core type -> VHDL Type
- vsTypes_ :: TypeMap,
+ vsTypes_ :: TypeMap,
+ -- | A map of vector Core type -> VHDL type function
+ vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
- vsSignatures_ :: SignatureMap
+ vsSignatures_ :: SignatureMap,
+ -- | A map of Vector HsFunctions -> VHDL function call
+ vsNameTable_ :: NameTable
}
-- Derive accessors
}
-- Derive accessors