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Generate proper VHDL for top level bindings with no arguments.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index b9db66a485220276f060c18edcb9c1419efa1fa3..b4c1d6981c2f757df4fb7c5049375aa4845bcb59 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-13,6
+13,7
@@
import qualified Data.Accessor.Template
-- GHC API imports
import qualified Type
import qualified CoreSyn
-- GHC API imports
import qualified Type
import qualified CoreSyn
+import qualified HscTypes
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
@@
-40,7
+41,7
@@
instance Ord OrdType where
data HType = StdType OrdType |
ADTType String [HType] |
data HType = StdType OrdType |
ADTType String [HType] |
- VecType
Int
HType |
+ VecType
OrdType
HType |
SizedWType Int |
RangedWType Int |
SizedIType Int |
SizedWType Int |
RangedWType Int |
SizedIType Int |
@@
-66,12
+67,11
@@
data TypeState = TypeState {
vsTypeDecls_ :: [AST.PackageDecItem],
-- | A map of vector Core type -> VHDL type function
vsTypeFuns_ :: TypeFunMap,
vsTypeDecls_ :: [AST.PackageDecItem],
-- | A map of vector Core type -> VHDL type function
vsTypeFuns_ :: TypeFunMap,
- vsTfpInts_ :: TfpIntMap
+ vsTfpInts_ :: TfpIntMap,
+ vsHscEnv_ :: HscTypes.HscEnv
}
-- Derive accessors
$( Data.Accessor.Template.deriveAccessors ''TypeState )
}
-- Derive accessors
$( Data.Accessor.Template.deriveAccessors ''TypeState )
--- Define an empty TypeState
-emptyTypeState = TypeState Map.empty [] Map.empty Map.empty
-- Define a session
type TypeSession = State.State TypeState
-- Define a session
type TypeSession = State.State TypeState