- ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMap, -- A mapping of the function result to port names
- ent_decl :: Maybe AST.EntityDec -- The actual entity declaration. Can be empty for builtin functions.
+ ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
+ ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
+} deriving (Show);
+
+-- A orderable equivalent of CoreSyn's Type for use as a map key
+newtype OrdType = OrdType { getType :: Type.Type }
+instance Eq OrdType where
+ (OrdType a) == (OrdType b) = Type.tcEqType a b
+instance Ord OrdType where
+ compare (OrdType a) (OrdType b) = Type.tcCmpType a b
+
+-- A map of a Core type to the corresponding type name
+type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
+
+-- A map of a Haskell function to a hardware signature
+type SignatureMap = Map.Map String Entity
+
+data VHDLSession = VHDLSession {
+ -- | A map of Core type -> VHDL Type
+ vsTypes_ :: TypeMap,
+ -- | A map of HsFunction -> hardware signature (entity name, port names,
+ -- etc.)
+ vsSignatures_ :: SignatureMap