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Pulled genZipWithCall into VHDLSession monad
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index a5d1569eb5728ebce6ec43223f5446674383bf9e..3a8bce12f88e4fef661449443dd72a4d0c05e20a 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-12,6
+12,7
@@
import qualified Data.Accessor.Template
-- GHC API imports
import qualified Type
-- GHC API imports
import qualified Type
+import qualified CoreSyn
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
-- ForSyDe imports
import qualified ForSyDe.Backend.VHDL.AST as AST
@@
-30,8
+31,8
@@
type VHDLSignalMap = HsValueMap VHDLSignalMapElement
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
-- ports.
data Entity = Entity {
ent_id :: AST.VHDLId, -- The id of the entity
- ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
- ent_res :: VHDLSignalMap -- A mapping of the function result to port names
+ ent_args :: [VHDLSignalMap
Element
], -- A mapping of each function argument to port names
+ ent_res :: VHDLSignalMap
Element
-- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
@@
-42,29
+43,41
@@
instance Ord OrdType where
compare (OrdType a) (OrdType b) = Type.tcCmpType a b
-- A map of a Core type to the corresponding type name
compare (OrdType a) (OrdType b) = Type.tcCmpType a b
-- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map OrdType (AST.VHDLId,
AST.TypeDec
)
+type TypeMap = Map.Map OrdType (AST.VHDLId,
Either AST.TypeDef AST.SubtypeIn
)
--- A map of
a Haskell function to a hardware signature
-type
SignatureMap = Map.Map HsFunction Entity
+-- A map of
Elem types to the corresponding VHDL Id for the Vector
+type
ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
--- A map of a builtin function to VHDL function builder
-type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
+-- A map of a vector Core type to the coressponding VHDL functions
+type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+
+-- A map of a Haskell function to a hardware signature
+type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-data VHDLS
ession = VHDLSession
{
+data VHDLS
tate = VHDLState
{
-- | A map of Core type -> VHDL Type
-- | A map of Core type -> VHDL Type
- vsTypes_ :: TypeMap,
+ vsTypes_ :: TypeMap,
+ -- | A map of Elem types -> VHDL Vector Id
+ vsElemTypes_ :: ElemTypeMap,
+ -- | A map of vector Core type -> VHDL type function
+ vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
vsSignatures_ :: SignatureMap
}
-- Derive accessors
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
vsSignatures_ :: SignatureMap
}
-- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLS
ession
)
+$( Data.Accessor.Template.deriveAccessors ''VHDLS
tate
)
-- | The state containing a VHDL Session
-- | The state containing a VHDL Session
-type VHDLS
tate = State.State VHDLSession
+type VHDLS
ession = State.State VHDLState
-- | A substate containing just the types
type TypeState = State.State TypeMap
-- | A substate containing just the types
type TypeState = State.State TypeMap
+type Builder = Either ([AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, Builder )
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: