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Pulled genZipWithCall into VHDLSession monad
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index 2538158d10a1c31117f28c30812ee4d9017571e5..3a8bce12f88e4fef661449443dd72a4d0c05e20a 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-54,12
+54,7
@@
type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-- A map of a Haskell function to a hardware signature
type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-type Builder = Either ([AST.Expr] -> AST.Expr) (Int -> Entity -> [AST.VHDLId] -> AST.GenerateSm)
-
--- A map of a builtin function to VHDL function builder
-type NameTable = Map.Map String (Int, Builder )
-
-data VHDLSession = VHDLSession {
+data VHDLState = VHDLState {
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A map of Elem types -> VHDL Vector Id
-- | A map of Core type -> VHDL Type
vsTypes_ :: TypeMap,
-- | A map of Elem types -> VHDL Vector Id
@@
-68,18
+63,21
@@
data VHDLSession = VHDLSession {
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
vsTypeFuns_ :: TypeFunMap,
-- | A map of HsFunction -> hardware signature (entity name, port names,
-- etc.)
- vsSignatures_ :: SignatureMap,
- -- | A map of Vector HsFunctions -> VHDL function call
- vsNameTable_ :: NameTable
+ vsSignatures_ :: SignatureMap
}
-- Derive accessors
}
-- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLS
ession
)
+$( Data.Accessor.Template.deriveAccessors ''VHDLS
tate
)
-- | The state containing a VHDL Session
-- | The state containing a VHDL Session
-type VHDLS
tate = State.State VHDLSession
+type VHDLS
ession = State.State VHDLState
-- | A substate containing just the types
type TypeState = State.State TypeMap
-- | A substate containing just the types
type TypeState = State.State TypeMap
+type Builder = Either ([AST.Expr] -> VHDLSession AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> VHDLSession AST.GenerateSm)
+
+-- A map of a builtin function to VHDL function builder
+type NameTable = Map.Map String (Int, Builder )
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: