ent_id :: AST.VHDLId, -- The id of the entity
ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
ent_res :: VHDLSignalMap -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key
ent_id :: AST.VHDLId, -- The id of the entity
ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
ent_res :: VHDLSignalMap -- A mapping of the function result to port names
} deriving (Show);
-- A orderable equivalent of CoreSyn's Type for use as a map key