projects
/
matthijs
/
master-project
/
cλash.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Don't inline alu.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index 9ae197c4e99ea9bfa80bb858227396c3522cd810..26ed823d904f35dd6653513f84cf2788e81ddac2 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-6,8
+6,11
@@
module VHDLTypes where
import qualified ForSyDe.Backend.VHDL.AST as AST
import FlattenTypes
import qualified ForSyDe.Backend.VHDL.AST as AST
import FlattenTypes
+import HsValueMap
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+-- signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's