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Don't generate ports for non-port signals.
[matthijs/master-project/cλash.git]
/
VHDLTypes.hs
diff --git
a/VHDLTypes.hs
b/VHDLTypes.hs
index 9ae197c4e99ea9bfa80bb858227396c3522cd810..1704bb874dc453a4475fe1657eb622e638ccb02c 100644
(file)
--- a/
VHDLTypes.hs
+++ b/
VHDLTypes.hs
@@
-7,7
+7,9
@@
import qualified ForSyDe.Backend.VHDL.AST as AST
import FlattenTypes
import FlattenTypes
-type VHDLSignalMap = SignalMap (AST.VHDLId, AST.TypeMark)
+-- | A mapping from a haskell structure to the corresponding VHDL port
+-- signature, or Nothing for values that do not translate to a port.
+type VHDLSignalMap = SignalMap (Maybe (AST.VHDLId, AST.TypeMark))
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's
-- A description of a VHDL entity. Contains both the entity itself as well as
-- info on how to map a haskell value (argument / result) on to the entity's