+ (sigName info)
+ ty = sigTy info
+
+ -- | Create the VHDL AST for an entity
+createEntityAST ::
+ HsFunction -- | The signature of the function we're working with
+ -> [VHDLSignalMap] -- | The entity's arguments
+ -> VHDLSignalMap -- | The entity's result
+ -> AST.EntityDec -- | The entity with the ent_decl filled in as well
+
+createEntityAST hsfunc args res =
+ AST.EntityDec vhdl_id ports
+ where
+ vhdl_id = mkEntityId hsfunc
+ ports = concatMap (mapToPorts AST.In) args
+ ++ mapToPorts AST.Out res
+ ++ clk_port
+ mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec]
+ mapToPorts mode m =
+ Maybe.catMaybes $ map (mkIfaceSigDec mode) (Foldable.toList m)
+ -- Add a clk port if we have state
+ clk_port = if hasState hsfunc
+ then
+ [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty]
+ else
+ []
+
+-- | Create a port declaration
+mkIfaceSigDec ::
+ AST.Mode -- | The mode for the port (In / Out)
+ -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
+ -> Maybe AST.IfaceSigDec -- | The resulting port declaration
+
+mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
+mkIfaceSigDec _ Nothing = Nothing
+
+-- | Generate a VHDL entity name for the given hsfunc
+mkEntityId hsfunc =
+ -- TODO: This doesn't work for functions with multiple signatures!
+ mkVHDLId $ hsFuncName hsfunc
+
+-- | Create an architecture for a given function
+createArchitecture ::
+ HsFunction -- | The function signature
+ -> FuncData -- | The function data collected so far
+ -> VHDLState ()
+
+createArchitecture hsfunc fdata =
+ let func = flatFunc fdata in
+ case func of
+ -- Skip (builtin) functions without a FlatFunction
+ Nothing -> do return ()
+ -- Create an architecture for all other functions
+ Just flatfunc -> do
+ let sigs = flat_sigs flatfunc
+ let args = flat_args flatfunc
+ let res = flat_res flatfunc
+ let defs = flat_defs flatfunc
+ let entity_id = Maybe.fromMaybe
+ (error $ "Building architecture without an entity? This should not happen!")
+ (getEntityId fdata)
+ -- Create signal declarations for all signals that are not in args and
+ -- res
+ let sig_decs = Maybe.catMaybes $ map (mkSigDec . snd) sigs
+ -- Create concurrent statements for all signal definitions
+ statements <- mapM (mkConcSm sigs) defs
+ let procs = map mkStateProcSm (getOwnStates hsfunc flatfunc)
+ let procs' = map AST.CSPSm procs
+ let arch = AST.ArchBody (mkVHDLId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
+ setArchitecture hsfunc arch