tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
mkUseAll ["IEEE", "std_logic_1164"],
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
mkUseAll ["IEEE", "std_logic_1164"],
type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
subProgSpecs = concat (map subProgSpec tyfun_decls)
subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
subProgSpecs = concat (map subProgSpec tyfun_decls)
subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
--[(SignalId, SignalInfo)]
CoreSyn.CoreBndr
-> VHDLState VHDLSignalMapElement
--[(SignalId, SignalInfo)]
CoreSyn.CoreBndr
-> VHDLState VHDLSignalMapElement
-> [VHDLSignalMapElement] -- | The entity's arguments
-> VHDLSignalMapElement -- | The entity's result
-> AST.EntityDec -- | The entity with the ent_decl filled in as well
-> [VHDLSignalMapElement] -- | The entity's arguments
-> VHDLSignalMapElement -- | The entity's result
-> AST.EntityDec -- | The entity with the ent_decl filled in as well
AST.EntityDec vhdl_id ports
where
-- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
AST.EntityDec vhdl_id ports
where
-- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
ports = Maybe.catMaybes $
map (mkIfaceSigDec AST.In) args
++ [mkIfaceSigDec AST.Out res]
ports = Maybe.catMaybes $
map (mkIfaceSigDec AST.In) args
++ [mkIfaceSigDec AST.Out res]
-> VHDLState AST.ArchBody -- ^ The architecture for this function
createArchitecture (fname, expr) = do
-> VHDLState AST.ArchBody -- ^ The architecture for this function
createArchitecture (fname, expr) = do
- --signaturemap <- getA vsSignatures
- --let signature = Maybe.fromMaybe
- -- (error $ "Generating architecture for function " ++ (prettyShow hsfunc) ++ "without signature? This should not happen!")
- -- (Map.lookup hsfunc signaturemap)
- let entity_id = mkVHDLBasicId $ bndrToString fname
+ signaturemap <- getA vsSignatures
+ let signature = Maybe.fromMaybe
+ (error $ "Generating architecture for function " ++ (pprString fname) ++ "without signature? This should not happen!")
+ (Map.lookup fname signaturemap)
+ let entity_id = ent_id signature
-- Strip off lambda's, these will be arguments
let (args, letexpr) = CoreSyn.collectBinders expr
-- There must be a let at top level
-- Strip off lambda's, these will be arguments
let (args, letexpr) = CoreSyn.collectBinders expr
-- There must be a let at top level
- -- Create signal declarations for all internal and state signals
- sig_dec_maybes <- mapM (mkSigDec' . fst) binds
+ -- Create signal declarations for all binders in the let expression, except
+ -- for the output port (that will already have an output port declared in
+ -- the entity).
+ sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
where
procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
where
procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
-- | Transforms a core binding into a VHDL concurrent statement
mkConcSm ::
(CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
-- | Transforms a core binding into a VHDL concurrent statement
mkConcSm ::
(CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
- -> VHDLState AST.ConcSm -- ^ The corresponding VHDL component instantiation.
+ -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
+
+
+-- Ignore Cast expressions, they should not longer have any meaning as long as
+-- the type works out.
+mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr)
mkConcSm (bndr, app@(CoreSyn.App _ _))= do
let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
mkConcSm (bndr, app@(CoreSyn.App _ _))= do
let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
case Var.globalIdVarDetails f of
IdInfo.DataConWorkId dc ->
-- It's a datacon. Create a record from its arguments.
-- First, filter out type args. TODO: Is this the best way to do this?
-- The types should already have been taken into acocunt when creating
-- the signal, so this should probably work...
case Var.globalIdVarDetails f of
IdInfo.DataConWorkId dc ->
-- It's a datacon. Create a record from its arguments.
-- First, filter out type args. TODO: Is this the best way to do this?
-- The types should already have been taken into acocunt when creating
-- the signal, so this should probably work...
- let assigns = zipWith mkassign labels valargs
- let block_id = bndrToVHDLId bndr
- let block = AST.BlockSm block_id [] (AST.PMapAspect []) [] assigns
- return $ AST.CSBSm block
+ return $ zipWith mkassign labels valargs
funSignatures <- getA vsNameTable
case (Map.lookup (bndrToString f) funSignatures) of
Just (arg_count, builder) ->
funSignatures <- getA vsNameTable
case (Map.lookup (bndrToString f) funSignatures) of
Just (arg_count, builder) ->
sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
func = builder sigsNames
src_wform = AST.Wform [AST.WformElem func Nothing]
dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
in
sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
func = builder sigsNames
src_wform = AST.Wform [AST.WformElem func Nothing]
dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
in
Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
IdInfo.NotGlobalId -> do
signatures <- getA vsSignatures
Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
IdInfo.NotGlobalId -> do
signatures <- getA vsSignatures
let
signature = Maybe.fromMaybe
(error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
let
signature = Maybe.fromMaybe
(error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
-- Add a clk port if we have state
--clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
-- Add a clk port if we have state
--clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
--- GHC generates some funny "r = r" bindings in let statements before
--- simplification. This outputs some dummy ConcSM for these, so things will at
--- least compile for now.
-mkConcSm (bndr, CoreSyn.Var _) = return $ AST.CSPSm $ AST.ProcSm (mkVHDLBasicId "unused") [] []
-
-- A single alt case must be a selector. This means thee scrutinee is a simple
-- variable, the alternative is a dataalt with a single non-wild binder that
-- is also returned.
-- A single alt case must be a selector. This means thee scrutinee is a simple
-- variable, the alternative is a dataalt with a single non-wild binder that
-- is also returned.
Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
_ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
_ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
return $ Just $ (Arrow.second Right) res
-- "SizedWord" -> do
-- res <- mk_vector_ty (sized_word_len ty) ty
-- return $ Just $ (Arrow.second Left) res
"RangedWord" -> do
return $ Just $ (Arrow.second Right) res
-- "SizedWord" -> do
-- res <- mk_vector_ty (sized_word_len ty) ty
-- return $ Just $ (Arrow.second Left) res
"RangedWord" -> do
return $ Just $ (Arrow.second Right) res
-- Create a custom type from this tycon
otherwise -> mk_tycon_ty tycon args
return $ Just $ (Arrow.second Right) res
-- Create a custom type from this tycon
otherwise -> mk_tycon_ty tycon args
- let ty_id = mkVHDLExtId $ "vector_0_to_" ++ (show len) ++ "-" ++ (show el_ty_tm)
- let range = AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
+ let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
+ let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
case existing_elem_ty of
Just t -> do
let ty_def = AST.SubtypeIn t (Just range)
return (ty_id, ty_def)
Nothing -> do
let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
case existing_elem_ty of
Just t -> do
let ty_def = AST.SubtypeIn t (Just range)
return (ty_id, ty_def)
Nothing -> do
- let vec_id = mkVHDLExtId $ "vector_" ++ (show el_ty_tm)
- let vec_def = AST.TDA $ AST.UnconsArrayDef [naturalTM] el_ty_tm
+ let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId el_ty_tm)
+ let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] el_ty_tm
let ty_def = AST.SubtypeIn vec_id (Just range)
return (ty_id, ty_def)
mk_natural_ty ::
Int -- ^ The minimum bound (> 0)
-> Int -- ^ The maximum bound (> minimum bound)
let ty_def = AST.SubtypeIn vec_id (Just range)
return (ty_id, ty_def)
mk_natural_ty ::
Int -- ^ The minimum bound (> 0)
-> Int -- ^ The maximum bound (> minimum bound)
-- Extracts the string version of the name
nameToString :: Name.Name -> String
nameToString = OccName.occNameString . Name.nameOccName
-- Extracts the string version of the name
nameToString :: Name.Name -> String
nameToString = OccName.occNameString . Name.nameOccName