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Add (non-working) support for SizedWord literals.
[matthijs/master-project/cλash.git]
/
VHDL.hs
diff --git
a/VHDL.hs
b/VHDL.hs
index 1d605ea7de71b1279ce051e5f675eb1aa7c193c8..8ae351611a6201dfd8a6c7dc7119d916e3961616 100644
(file)
--- a/
VHDL.hs
+++ b/
VHDL.hs
@@
-50,7
+50,8
@@
createDesignFiles flatfuncmap =
ty_decls = Map.elems (final_session ^. vsTypes)
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
ty_decls = Map.elems (final_session ^. vsTypes)
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
- mkUseAll ["IEEE", "std_logic_1164"]
+ mkUseAll ["IEEE", "std_logic_1164"],
+ mkUseAll ["IEEE", "numeric_std"]
]
full_context =
mkUseAll ["work", "types"]
]
full_context =
mkUseAll ["work", "types"]