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Enable the DontCare value for Bit again.
[matthijs/master-project/cλash.git]
/
VHDL.hs
diff --git
a/VHDL.hs
b/VHDL.hs
index 57bebfc12ab0265369ecb7028a6a8740c579d2d6..1c7eba9ea2e848fbca70c620357e1b0e9fb09f85 100644
(file)
--- a/
VHDL.hs
+++ b/
VHDL.hs
@@
-205,6
+205,10
@@
mkConcSm sigs (UncondDef src dst) = do
case expr of
(EqLit id lit) ->
(mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
case expr of
(EqLit id lit) ->
(mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
+ (Literal lit) ->
+ AST.PrimLit lit
+ (Eq a b) ->
+ (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
mkConcSm sigs (CondDef cond true false dst) = do
let cond_expr = mkIdExpr sigs cond
mkConcSm sigs (CondDef cond true false dst) = do
let cond_expr = mkIdExpr sigs cond
@@
-316,7
+320,7
@@
vhdl_ty_maybe ty =
let name = TyCon.tyConName tycon in
-- TODO: Do something more robust than string matching
case Name.getOccString name of
let name = TyCon.tyConName tycon in
-- TODO: Do something more robust than string matching
case Name.getOccString name of
- "Bit" -> Just
bit
_ty
+ "Bit" -> Just
std_logic
_ty
otherwise -> Nothing
otherwise -> Nothing
otherwise -> Nothing
otherwise -> Nothing