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Don't generate ports for non-port signals.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 9ce7206c9df9bd841bd0c5a4e7cccabe1d392b3f..f875dd6b3ad5bee7876fcd624104940ab1937101 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-54,7
+54,7
@@
main =
--core <- GHC.compileToCoreSimplified "Adders.hs"
core <- GHC.compileToCoreSimplified "Adders.hs"
--liftIO $ printBinds (cm_binds core)
--core <- GHC.compileToCoreSimplified "Adders.hs"
core <- GHC.compileToCoreSimplified "Adders.hs"
--liftIO $ printBinds (cm_binds core)
- let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["
sfull_adder
"]
+ let binds = Maybe.mapMaybe (findBind (cm_binds core)) ["
dff
"]
liftIO $ putStr $ prettyShow binds
-- Turn bind into VHDL
let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
liftIO $ putStr $ prettyShow binds
-- Turn bind into VHDL
let (vhdl, sess) = State.runState (mkVHDL binds) (VHDLSession core 0 Map.empty)
@@
-72,13
+72,7
@@
main =
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
- -- Extract the library units generated from all the functions in the
- -- session.
- funcs <- getFuncs
- let units = concat $ map VHDL.getLibraryUnits funcs
- return $ AST.DesignFile
- []
- units
+ VHDL.getDesignFile
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =
@@
-215,7
+209,7
@@
data BuiltIn = BuiltIn String [PortMap] PortMap
-- | Map a port specification of a builtin function to a VHDL Signal to put in
-- a VHDLSignalMap
toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
-- | Map a port specification of a builtin function to a VHDL Signal to put in
-- a VHDLSignalMap
toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
-toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+toVHDLSignalMap = fmap (\(name, ty) ->
Just
(VHDL.mkVHDLId name, ty))
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.