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Further reduce main and add a makeVHDL function.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 53befc228e6ef947107b72141d9cb7c713fd5606..ddd09fc340da9a401a24e1399c797de60c238234 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-42,10
+42,14
@@
import VHDLTypes
import qualified VHDL
main = do
import qualified VHDL
main = do
+ makeVHDL "Alu.hs" "salu"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
-- Load the module
-- Load the module
- core <- loadModule
"Adders.hs"
+ core <- loadModule
filename
-- Translate to VHDL
-- Translate to VHDL
- vhdl <- moduleToVHDL core [
"sfull_adder"
]
+ vhdl <- moduleToVHDL core [
name
]
-- Write VHDL to file
writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
-- Write VHDL to file
writeVHDL vhdl "../vhdl/vhdl/output.vhdl"