+ modFuncs nameFlatFunction
+ modFuncs VHDL.createEntity
+ modFuncs VHDL.createArchitecture
+ VHDL.getDesignFile
+
+-- | Write the given design file to the given file
+writeVHDL :: AST.DesignFile -> String -> IO ()
+writeVHDL = ForSyDe.Backend.VHDL.FileIO.writeDesignFile
+
+-- | Loads the given file and turns it into a core module.
+loadModule :: String -> IO HscTypes.CoreModule
+loadModule filename =
+ defaultErrorHandler defaultDynFlags $ do
+ runGhc (Just libdir) $ do
+ dflags <- getSessionDynFlags
+ setSessionDynFlags dflags
+ --target <- guessTarget "adder.hs" Nothing
+ --liftIO (print (showSDoc (ppr (target))))
+ --liftIO $ printTarget target
+ --setTargets [target]
+ --load LoadAllTargets
+ --core <- GHC.compileToCoreSimplified "Adders.hs"
+ core <- GHC.compileToCoreSimplified filename
+ return core
+
+-- | Extracts the named binds from the given module.
+findBinds :: HscTypes.CoreModule -> [String] -> [CoreBind]
+findBinds core names = Maybe.mapMaybe (findBind (cm_binds core)) names