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Add port maps to component instantiations.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 37a812b2bceca493cf1e95824c6b7ea4b4484d4e..cccac4c08047178ec368a5a992d3c0eac48f4a0d 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-37,6
+37,7
@@
import HsValueMap
import Pretty
import Flatten
import FlattenTypes
import Pretty
import Flatten
import FlattenTypes
+import VHDLTypes
import qualified VHDL
main =
import qualified VHDL
main =
@@
-211,13
+212,20
@@
type PortMap = HsValueMap (String, AST.TypeMark)
-- | A consise representation of a builtin function
data BuiltIn = BuiltIn String [PortMap] PortMap
-- | A consise representation of a builtin function
data BuiltIn = BuiltIn String [PortMap] PortMap
+-- | Map a port specification of a builtin function to a VHDL Signal to put in
+-- a VHDLSignalMap
+toVHDLSignalMap :: HsValueMap (String, AST.TypeMark) -> VHDLSignalMap
+toVHDLSignalMap = fmap (\(name, ty) -> (VHDL.mkVHDLId name, ty))
+
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.
addBuiltIn :: BuiltIn -> VHDLState ()
addBuiltIn (BuiltIn name args res) = do
addFunc hsfunc
-- | Translate a concise representation of a builtin function to something
-- that can be put into FuncMap directly.
addBuiltIn :: BuiltIn -> VHDLState ()
addBuiltIn (BuiltIn name args res) = do
addFunc hsfunc
+ setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
builtin_funcs =
[
builtin_funcs =
[