projects
/
matthijs
/
master-project
/
cλash.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
Generate VHDL signals for internal signals and state.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index c037a1e24a0d30a8f97aeca69c815fa65ad9e97d..9cced3444d452607e3b8d35cc9b3ce631b6ee515 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-72,13
+72,7
@@
main =
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
- -- Extract the library units generated from all the functions in the
- -- session.
- funcs <- getFuncs
- let units = concat $ map VHDL.getLibraryUnits funcs
- return $ AST.DesignFile
- []
- units
+ VHDL.getDesignFile
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =
findBind :: [CoreBind] -> String -> Maybe CoreBind
findBind binds lookfor =