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Make createEntity preserve the Entity on builtin functions.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 841f63b892c2f330adfa88bca5c837cf5a7ada23..6a784251d3c310240fc657b8a0c183980cc80202 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-92,9
+92,10
@@
moduleToVHDL core list = do
-- Create entities and architectures for them
Monad.zipWithM processBind statefuls binds
modFuncs nameFlatFunction
-- Create entities and architectures for them
Monad.zipWithM processBind statefuls binds
modFuncs nameFlatFunction
- modFunc
s VHDL.createEntity
+ modFunc
Map $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
modFuncs VHDL.createArchitecture
modFuncs VHDL.createArchitecture
- VHDL.getDesignFiles
+ funcs <- getFuncs
+ return $ VHDL.getDesignFiles (map snd funcs)
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
@@
-387,7
+388,7
@@
addBuiltIn (BuiltIn name args res) = do
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
- entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
Nothing
builtin_funcs =
[
builtin_funcs =
[