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Remove getDesignFiles from the VHDLState monad.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 841f63b892c2f330adfa88bca5c837cf5a7ada23..5e36b3856b631666cc4fb62fb932631e21a33943 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-94,7
+94,8
@@
moduleToVHDL core list = do
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
- VHDL.getDesignFiles
+ funcs <- getFuncs
+ return $ VHDL.getDesignFiles (map snd funcs)
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
@@
-387,7
+388,7
@@
addBuiltIn (BuiltIn name args res) = do
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
- entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
Nothing
builtin_funcs =
[
builtin_funcs =
[