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Remove getDesignFiles from the VHDLState monad.
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 383c477282e04fa3429c153520cf13064eca1d0d..5e36b3856b631666cc4fb62fb932631e21a33943 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-94,7
+94,8
@@
moduleToVHDL core list = do
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
modFuncs nameFlatFunction
modFuncs VHDL.createEntity
modFuncs VHDL.createArchitecture
- VHDL.getDesignFiles
+ funcs <- getFuncs
+ return $ VHDL.getDesignFiles (map snd funcs)
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name